The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for forming a fine pattern in a semiconductor device using a quadruple patterning.
As semiconductor devices are continuously becoming highly integrated, micronization of various patterns, e.g., lines and space patterns, needed for forming circuits constituting a semiconductor device is accelerating.
However, there are limitations as to the micronization of patterns due to limitations of photolithography equipments, in particular, photo-exposure equipments. It is difficult for the current photo-exposure equipments to form a fine pattern having a line width smaller than 40 nm due to resolution limitations.
Therefore, a new type of technology which can form a fine pattern having dimensions below the limiting resolution by using the current photo-exposure equipments is desired. A pattern doubling technology using a spacer patterning is one of the most widely researched technology for forming a fine pattern up to now.
FIGS. 1A to 1G illustrate cross-sectional views of a typical method for forming a fine pattern by performing a pattern doubling technology using a spacer patterning. Referring to FIG. 1A, a typical pattern doubling process using a spacer patterning includes forming an etch target layer 11 over a substrate 10. A hard mask layer 12 including tetraethyl orthosilicate (TEOS) is formed over the etch target layer 11. A first polysilicon layer 13, an amorphous carbon layer 14, and a silicon oxynitride (SiON) layer 15 are formed over the hard mask layer 12. A bottom anti-reflective coating (BARC) layer 16 and a photoresist layer are formed over the silicon oxynitride layer 15. A photo-exposure and developing process using a mask is performed to form a photoresist pattern 17.
Referring to FIG. 1B, the bottom anti-reflective coating layer 16, the silicon oxynitride layer 15, the amorphous carbon layer 14 are etched using the photoresist pattern 17 as an etch barrier. The first polysilicon layer 13 is etched using the etched amorphous carbon layer 14 as an etch barrier to form a first polysilicon pattern 13A. Herein, portions of the exposed hard mask layer 12 are etched to an etch target of substantially the same thickness as that of a subsequent spacer oxide layer. Reference denotation 12A represents an etched hard mask layer 12A.
Meanwhile, the photoresist pattern 17 and remaining portions of the bottom anti-reflective coating layer 16, the silicon oxynitride layer 15, and the amorphous carbon layer 14 are mostly removed during the etching process.
Referring to FIG. 1C, a spacer oxide layer 18 is formed over the surface profile of the substrate structure. Herein, the spacer oxide layer 18 is formed to a thickness which can fill the etched regions of the etched hard mask layer 12A.
Referring to FIG. 1D, a second polysilicon layer 19 is formed over the substrate structure. Herein, the second polysilicon layer 19 is formed to a thickness sufficient to, for example, completely fill spaces between the first polysilicon pattern 13A.
Referring to FIG. 1E, the second polysilicon layer 19 is recessed until the spacer oxide layer 18 is exposed. Herein, an etch-back process or a chemical mechanical polishing (CMP) process may be performed to form a recessed second polysilicon pattern 19A.
Referring to FIG. 1F, the spacer oxide layer 18 is selectively etched to form a first etched spacer oxide pattern 18A. Herein, the spacer oxide layer 18 is etched in a manner that the first etched spacer oxide pattern 18A remains in regions to be etched during a subsequent etching of the etched hard mask layer 12A. Portions of the first polysilicon pattern 13A and the second polysilicon pattern 19A are also etched while etching the spacer oxide layer 18. Reference denotations 13B and 19B represent an etched first polysilicon pattern 13B and an etched second polysilicon pattern 19B, respectively. Consequently, the etched first polysilicon pattern 13B and the etched second polysilicon pattern 19B are alternately formed.
Referring to FIG. 1G, the first etched spacer oxide pattern 18A and the etched hard mask layer 12A are etched using the etched first polysilicon pattern 13B and the etched second polysilicon pattern 19B as an etch barrier to form a second etched spacer oxide pattern 18B and a hard mask 12B. Reference denotations 13C and 19C represent a remaining first polysilicon pattern 13C and a remaining second polysilicon pattern 19C, respectively.
Although not illustrated, the etch target layer 11 is etched using the hard mask 12B as an etch barrier. Material layers remaining over the etched etch target layer 11 are removed to complete a patterning process on the etch target layer 11.
As described above, a fine pattern having a line width of approximately 20 nm may be embodied by performing the pattern doubling technology using the spacer patterning method.
However, when a fine pattern having a line width of less than 20 nm is required due to larger scale integration, limitations may arise from the limiting resolution of photo-exposure equipments even if the pattern doubling technology is used. Thus, a quadruple patterning technology has been introduced to overcome such limitations.
The currently introduced quadruple patterning technology includes repeatedly performing the typical spacer patterning two times. That is, the processes shown in FIGS. 1A to 1F are performed and then the processes shown in FIGS. 1C to 1G are performed once again.
The typical quadruple patterning technology may not be able to guarantee pattern fidelity and space uniformity because a second spacer is formed when the profile of a partition pattern patterned by a first spacer is unstable, e.g., when horns are generated at the uppermost portion of the pattern.